1. Field of the Invention
The embodiments described herein are directed to non-volatile memory devices, and more particularly to a non-volatile memory device comprising a single polysilicon gate layer that is compatible with CMOS processing techniques.
2. Background of the Invention
Many non-volatile semiconductor memories are based on the well known MOS-type structure. In other words, they comprise a gate structure separated from a substrate by a dielectric layer. Diffusion regions are implanted in the substrate under the corners of the gate structure. When the appropriate voltages are applied to the diffusion regions and the control gate, a channel can be created in the upper layers of the substrate between the diffusion regions and under the gate structure. Carriers, e.g., electrons, can travel the channel between the diffusion regions.
If a sufficient field component is present in the direction of the gate structure, the carriers, e.g., electrons, can be attracted to the gate structure. If the electrons have enough energy to overcome the barrier height of the dielectric layer, then these carriers can be injected through the dielectric layer.
For example, FIG. 1 is a diagram illustrating a conventional floating gate memory device 100. It will be understood that such a floating gate device can be the basic memory structure of a conventional flash memory device. Floating gate device 100 comprises of substrate 102 into which diffusion region 104 and 106 have been implanted. In the example of FIG. 1, device 100 is an NMOS device, meaning that substrate 102 is a P-type substrate while diffusion regions 104 and 106 are N+-type diffusion regions. It will be understood that certain memory devices can also make use of PMOS structures in which substrate 102 is an N-type substrate and diffusion regions 104 and 106 are P+-type diffusion regions.
A dielectric layer 110 is then formed over the substrate between diffusion regions 104 and 106. This dielectric layer is often a silicon dioxide dielectric layer and can be referred to as the tunnel oxide layer. A floating gate 112 is formed on top of dielectric layer 110. Floating gate 112 is typically formed from a polysilicon layer that is deposited on top of substrate 102 and etched to the appropriate dimensions. An inter-dielectric layer 114 is then formed over floating gate 112, and a control gate 116 is then formed on inter-dielectric layer 114. As with floating gate 112, control gate 116 is typically formed from a polysilicon layer that is etched to the appropriate dimensions.
When the appropriate voltages are applied to control gate 116 and diffusion regions 104 and 106, a channel can be formed in channel region 108 of substrate 102. The voltage applied to control gate 116 will couple with floating gate 112 to create the field component necessary to attract carriers in channel region 108 to floating gate 112. It will be understood, that the coupling between control gate 116 and floating gate 112 is dependent on the voltage applied to control gate 116 as well as the dimensions associated with control gate 116, inter-dielectric layer 114, and floating gate 112.
It will further be understood that density and cost are important driving factors in non-volatile semiconductor memory technology. The ever-expanding uses for non-volatile semiconductor memories require such memories to be mass-producible at low cost. Further, the requirements of new applications for non-volatile semiconductor memories require increased capacity, and a decreased footprint.
Device 100 of FIG. 1 presents several problems in this regard. First, because both floating gate 112 and control gate 116 are formed from polysilicon layers, device 100 is fabricated using what is termed a double poly process. This makes fabrication of device 100 incompatible with conventional CMOS techniques, which are single poly processes. As a result, special processes are required in order to fabricate device 100. Second, the need for diffusion regions 104 and 106, and for sufficient coupling between control gate 116 and floating gate 112, limits the minimum dimensions that can be achieved for device 100. For example, a certain active area is required in order to provide proper operation.
FIG. 2 is a diagram illustrating a conventional floating gate device 200 that overcomes some of the limitations associated with device 100 of FIG. 1. As can be seen, device 200 comprises a substrate 102 and diffusion regions 104, 106, and 116 implanted therein. Floating gate 112 is then formed over dielectric layer 110, which is formed over the substrate 102. In device 200, however, control gate 114 is also formed on dielectric 110 separated from floating gate 112 as illustrated. Voltages applied to control gate 114 can still couple with floating gate 112 to thereby induce carriers in channel region 108 to tunnel through dielectric layer 110 onto floating gate 112.
Advantageously, floating gate 112 and control gate 114 can be formed using a single poly process, which can make fabrication of device 200 compatible with conventional CMOS techniques; however, device 200 does not overcome the minimum dimension restrictions associated with device 100.